This application is based on Japanese Patent Application 2001-020261, filed on Jan. 29, 2001, the entire contents of which are incorporated herein by reference.
A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device suitable for forming two types of field effect transistors (FET) having different gate lengths.
B) Description of the Related Art
To meet the requirements for high speed operations of a semiconductor integrated circuit, techniques of narrowing an electrode width or a patterning width of photolithography over a process limit are desired. In a ultra high speed semiconductor device (such as a general logic circuit device and a logic circuit mixed with DRAM) having a static random access memory (SRAM) circuit and a logic circuit, if the logic circuit only is to be speeded up, it is necessary to shorten the gate length of FET""s of the logic circuit. To this end, a reticle is required to be revised by a new edition.
For a stepper using KrF excimer laser at a wavelength of 248 nm, it is difficult to form resist patterns having a line width of 0.2 xcexcm at a standard deviation of 0.01 xcexcm or smaller.
Techniques of reducing a patterning line width over a process limit of photolithography are disclosed in JP-A-7-22396, JP-A-9-237777 and JP-9-251988. According to the techniques disclosed in JP-7-22396, an etching mask pattern itself is side-etched to narrow a line width of the mask pattern. According to the techniques disclosed in JP-A-9-237777 and JP-A-9-251988, a resist pattern is made narrower by isotropically etching the resist pattern.
FIG. 7A is a plan view showing an FET on a logic circuit section. A ate electrode 202 crosses an active region 200. The gate electrode 202 is patterned by using a resist pattern obtained by narrowing a resist pattern 201 made through the exposure and development. Since the gate length (width in the vertical direction in FIG. 7A) of the gate electrode 202 can be shortened, FET can be speeded up.
FIG. 7B is a plan view of FET""s on an SRAM section. Two active regions 210 and 211 are disposed in parallel to each other. Gate electrodes 213 and 215 cross the active region 210, and gate electrodes 217 and 219 cross the active region 211. The gate electrode 217 is disposed on a straight line extended from the gate electrode 213, and one end of the gate electrode 217 faces one end of the gate electrode 213. The relative positional relation between the gate electrodes 215 and 219 is the same as that between the gate electrodes 213 and 217.
The gate electrodes 213, 215, 217 and 219 are patterned by using a resist mask pattern obtained by narrowing resist patterns 212, 214, 216 and 218 made through the exposure and development. Generally, in order to raise the integration degree of an SRAM section, a distance between the end of the resist pattern 212 and the end of the resist pattern 216 is set to a minimum patterning width of the exposure and development processes.
As the resist patterns 212 and 216 are narrowed, the distance between the ends becomes longer. In the example shown in FIG. 7B, as the end of the gate electrode 213 retracts and this retraction amount becomes large, the end of the gate electrode 213 enters the active region 210 in some cases. If the active regions 210 and 211 are disposed more spaced apart from each other by considering the retraction of the ends of gate electrodes, a chip area becomes large.
It is an object of the present invention to provide a semiconductor device capable of speeding up FET""s on a logic circuit section and highly integrating an SRAM section, and its manufacture method.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a gate electrode conductive film on a surface of a semiconductor substrate on which first and second sections are defined, field effect transistors having channel lengths different from each other being respectively formed on the first and second sections; forming first and second gate mask patterns made of a first insulating material on the gate electrode conductive film on the first and second sections; forming sidewall spacers on sidewalls of the first and second gate mask patterns, the sidewall spacer being made of a second insulating material having an etching resistance different from the first insulating material; covering the second section with a mask pattern; removing the sidewall spacer on the sidewall of the first gate mask pattern by using the mask pattern as a mask; removing the mask pattern; and etching the gate electrode conductive film to leave first and second gate electrodes on the first and second sections, by using as a mask the first and second gate mask patterns and the sidewall spacer left on the sidewall of the second gate mask pattern.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a first field effect transistor having a gate electrode formed on a first section of a semiconductor substrate; a second field effect transistor having a gate electrode formed on a second section of said semiconductor substrate; and a ridge structure made of insulating material formed on an upper surface of the gate electrode of said second field effect transistor, said ridge structure extending along side edges of the gate electrode.
When the gate electrode is patterned, the ridge structure is used as an etching mask, so that the gate electrode can be broadened by a width of the ridge structure and can also be elongated. It is therefore possible to make the gate length of the field effect transistor on the second section different from the gate length of the field effect transistor on the first section.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a gate electrode conductive film on a surface of a semiconductor substrate on which first and second sections are defined, field effect transistors having channel lengths different from each other being formed on the first and second sections; covering an upper surface of the gate electrode conductive film on the second section with a first mask film made of a first material; forming a second mask film on the gate electrode conductive film on the first section and on the first mask, the second mask being made of second material having an etching resistance different from the first material; forming resist patterns corresponding to gate electrodes on the second mask film on the first and second sections; etching the second and first mask films to leave a first gate mask pattern of the second mask film on the first section and a second gate mask pattern having a lamination structure of the first and second mask films on the second section, by using the resist patterns as a mask; side-etching a portion of the second mask film constituting the first and second gate mask patterns; and etching the gate electrode conductive film to leave first and second gate electrodes on the first and second sections, by using the first and second gate mask patterns as a mask.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a first field effect transistor having a gate electrode formed on a first section of a semiconductor substrate; a second field effect transistor having a gate electrode formed on a second section of said semiconductor substrate; a first film made of a first material and disposed on the gate electrode of said second field effect transistor, an outer periphery of said first film being aligned with side edges of the underlying gate electrode; a second film disposed on said first film, an outer periphery of said second film positioning inside the outer periphery of said first film, and said second film being made of a second material having an etching resistance different from the first material; and a third film disposed on the gate electrode of said first field effect transistor, an outer periphery of said third film being aligned with side edges of the underlying gate electrode, said third film being made of the second material.
When the gate electrodes are patterned, the third film is used as an etching mask on the first section, and the first film is used as an etching mask on the second section. It is therefore possible to make the gate length of the field effect transistor on the second section different from the gate length of the field effect transistor on the first section.
As described above, on one section of a substrate surface, the gate length of FET can be shortened more than the minimum patterning line width of photolithography, and on another section, the gate length of FET can be made approximately equal to the minimum patterning line width of photolithography. An operation speed of an integrated circuit on the section with the gate length being shortened can be raised. On the other section, even if the gate length is shortened, conventional design can be inherited.